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Announcing the RISE RISC-V Runners: free, native RISC-V CI on GitHub
by Ludovic Henry, RISE Today, we are excited to announce the Early Availability of the RISE RISC-V Runners, a free, managed GitHub Actions runner service that gives any open source...
Announcing the 2025 AI & RISC-V Gemini Credit Recipients
Posted by: Melissa Daniels, Google And the winners are… In September we sent out a call for proposals, looking for researchers and academics that would leverage AI to speed up...
A Glimpse Into V8 Development for RISC-V
Posted by: Florian Loitsch, Ji Qiu, Kasper Lund, Yahan Lu, Zhijin Zeng In 2020, Kim McMahon wrote a blog post where she announced the open-sourcing of V8 on RISC-V. At...
OpenJDK: Supercharging Vectorized Math with SLEEF
by Hamlin Li, Rivos The Java landscape is constantly evolving, with performance being a key area of focus. One of the most exciting recent developments is the introduction of the...
Tested on Real Silicon: Automating RISC-V Hardware-in-the-Loop
Contributed by Ariel D’Alessandro, Collabora TL;DR: As RISC-V adoption grows, the need for reliable, scalable hardware testing infrastructure becomes critical. To address this gap in the ecosystem the RISE Project...
OpenJDK: CMoveX & Vectorization
by Hamlin Li, Rivos In the ever-evolving landscape of software development, performance is paramount. For the Java platform, this means continuous innovation in the Just-In-Time (JIT) compiler to generate highly...
Easy Installation of Binary Python Packages on riscv64 Devices
by Mark Ryan, RIVOS Why can it be difficult to install Python packages on riscv64 devices? The Python Package Index (PyPI) offers both pure Python and binary packages. Binary packages,...
Project RP009: LLVM SPEC Optimization
by Mikhail R. Gadelha, Igalia S.L. Over the past eight months, Igalia has been working through RISE on the LLVM compiler, focusing on its RISC-V target. The goal is to...
Project RP004: Support for a 64-bit RISC-V Linux port of Rust to Tier-1
Motivation The Rust programming language community has a Target Tier Policy that defines the level of support and expectations for different platform ports. Tier-1 targets receive the highest level of...
Developer Spotlight | Meet Ekaitz Zarraga
In the RISE Developer Spotlight, our goal is to highlight and introduce valuable contributions from RISC-V community members who have achieved our Developer Appreciation award. With that, we would like...
Advancing Go on RISC-V: Progress Through the RISE Project
Authors: Ludovic Henry, Mark Ryan Since early 2024, the Go programming language has seen significant progress on the RISC-V architecture, largely due to ongoing efforts within the RISE Project and...
Working Group Lead Election Results
RISE has completed its 2025 election for working group leads. Congratulations to all of the new (and reelected) leads, and a big Thank You to the outgoing leads! Your work...
Fond Farewell to Calista Redmond, RISC-V Int’l CEO
The RISE Project wants to extend a special recognition of gratitude to Calista Redmond, the outgoing CEO for RISC-V International. Calista has been at the helm for RISC-V for nearly...
RISE 2024 End of Year Ecosystem Update
What a year this has been! With nearly a dozen RFPs in process and over €1m committed, RISE has been instrumental in enabling the RISC-V software ecosystem in 2024. To...
Working with Igalia to improve RISC-V LLVM Continuous Integration
by Alex Bradbury, Igalia S.L. The LLVM project provides a very widely used and actively developed suite of compiler and toolchain technologies: including Clang, the LLVM middle-end optimizer and backend...
Announcing the RISE RISC-V Developer Appreciation Pilot Program: Empowering Developers to Expand RISC-V’s Reach
by Barna Ibrahim, RIVOS At RISE, we’re always looking for ways to strengthen the RISC-V architecture and expand its adoption across the software ecosystem. To take this vision further, we’re...
RISE Discusses RISC-V Software Acceleration at RISC-V Taipei Day 2024
by Barna Ibrahim, RIVOS We just concluded a highly successful RISC-V Taipei Day, where the enthusiasm and engagement of the RISC-V community were evident. Attendees gathered in large numbers to...
Help us contribute to the RISC-V Optimization Guide
by Ludovic Henry, RIVOS In the world of computing, performance is key. As RISC-V continues to rise in popularity for its open standard instruction set architecture, achieving the highest performance...
Leveraging Scaleway to support the RISC-V Software Ecosystem
by Ludovic Henry, RIVOS Inc. At RISE, we have leveraged Scaleway’s RISC-V EM-RV1 offering to support major open-source projects like Adoptium, Go, AlmaLinux, and RockyLinux. Scaleway provides bare-metal RISC-V instances...
Stack-Clash security checker for RISC-V
by Alexey Merzlyakov, Samsung Research Introduction Security – is a very important factor of everyday computing. Vulnerabilities are becoming increasingly common in today’s digital world, propagating significant threats to organizations...
Happy Anniversary, RISE Project!
June 1 marks the first anniversary of the RISE Project. We began last year with 13 core organizations, with the stated goal to enable and improve the RISC-V software ecosystem....
Welcome to the RISE Project blog!
The RISE Project welcomes you to our blog! We intend to use this space to share what we are up to in the technical working groups and our sponsored RFPs, as well as the RISC-V...
