By Ashleigh Bustamante, Google
At the 2026 RISC-V Summit Europe in Bologna, Italy, the presence and influence of the RISE Project members were front and center, bridging the gap between hardware architecture and commercial-grade deployment across mobile, data center, automotive, and consumer electronics.
Key highlights from the summit involving RISE member companies and its governing board include:
Consolidating the Software Ecosystem & Standards
- Nathan Egge (Google) & Ludovic Henry (Qualcomm) presented on Advancing the RISC-V Software Ecosystem. Industry competitors are actively aligning on shared toolchains, runtimes, and operating system optimizations to drive rapid upstream software maturity and ensure broad commercial readiness.
- Greg Kroah-Hartman (The Linux Foundation) provided a candid look from the lead maintainer of the stable Linux kernel branch on how the RISC-V ecosystem can intentionally avoid the historic architecture fragmentation flaws that previously plagued x86 and ARM.
- Guodong Xu (SpacemiT) and Charlie Jenkins (Meta) dove into how engineers are explicitly implementing RVA23 support within the Linux kernel and seamlessly exposing those hardware instruction-set extensions up to user-facing applications.
Enterprise Cloud & Datacenter Readiness
- Radim Krčmář (Qualcomm) highlighted the newly introduced RISC-V Server Platform 1.0 specification, showing how standardizing firmware interfaces and boot processes allows enterprise operating systems to “just boot” regardless of the motherboard vendor.
- Jon Taylor (Canonical) mapped out the essential enterprise-class operating system blocks, container environments, and virtualization layers needed to turn raw custom silicon into operational, secure enterprise cloud infrastructure.
Hardware-Enforced Security & Isolation
- Andrew Dellow (Qualcomm) explained how a multi-tiered security approach—leveraging physical memory protection and advanced hardware isolation frameworks—enables reliable confidential computing models spanning from low-resource microcontrollers to hyper-scale cloud nodes.
- Haoyuan Liu (BOSC) demonstrated how robust, verifiable hardware isolation and data privacy can be cleanly achieved in zero-trust, multi-tenant cloud environments without relying on proprietary or closed-source extensions.
High-Performance Hardware & Silicon Co-Design
- Xu An (BOSC) & Yungang Bao (ICT CAS) outlined the practical engineering hurdles and design practices required to bridge the gap between academic open-source architecture and reliable, massive-scale industrial deployment for one of the world’s most prominent RISC-V core projects.
- Tor Jeremiassen (Google) & Yenkai Wang (Google) demonstrated how to leverage open-source MPACT tooling for rapid hardware-software co-design, which allows teams to write and test software long before their physical silicon is actually manufactured.
Automotive Safety & Consumer Applications
- Andreas Mauderer (BOSCH) & Zdenek Prikryl (Codasip) provided a practical architectural blueprint for the highly regulated automotive market, demonstrating how to balance the power of hardware customization with strict ISO 26262 functional safety certifications.
- Xiaogang Fan (SpacemiT) shifted the focus to mainstream consumer adoption, this session highlights the current state of consumer-ready computing on open silicon and explores how to build or port software for an optimized RISC-V user experience.
Panel Spotlight: Debating the Future of Software Enablement for RISC-V
- Moderator: Tom Gall (RISC-V International)
- Panelists: Greg Kroah-Hartman (Linux Foundation), Lars Bergstrom (Google), Paul Carpenter (Barcelona Supercomputing Center)
- Industry experts were brought together to dissect the current state of the software ecosystem—from low-power embedded up to High-Performance Computing (HPC)—while mapping out immediate priorities for the community.
For a deeper dive into the specific partnerships, presentations, and technical specs presented in Bologna, review the RISC-V Summit Europe 2026 Summit Overview.
