Author: Trevor Gamblin tgamblin@baylibre.com
In June 2025, RISC-V International joined the Yocto Project as a Platinum-level member, which signaled formal backing and oversight for RISC-V within the project. RISC-V is now a featured architecture in Yocto’s automated test matrix, which means that the entire Linux ecosystem benefits from early identification, reporting, and fixing of issues upstream. Meanwhile, RISE has been working hard to triage these issues, and to improve support for a variety of hardware platforms within the project, but this is only the beginning. Let’s take a look at RISC-V’s evolution in the Yocto Project and what the future holds.
What is the Yocto Project?
The Yocto Project is a collaborative ecosystem which provides tools and configurations to build customized Linux operating systems. This includes broad support for many architectures, with the flexibility to fine-tune the outputs and even write your own custom layers to achieve your project’s goals. The Yocto community includes contributors ranging from individual developers to some of the biggest companies and organizations from industry – RISC-V International is one of the latest to join the project. RISC-V is now a primary architecture in the Yocto Project, and this support means that both communities can make use of it to build the next generation of embedded Linux systems.
Yocto Before RISE: A Brief RISC-V Support Timeline
| Date | Yocto Layer | Milestone |
|---|---|---|
| October 2017 | meta-riscv | Layer created, qemuriscv64 Board Support Package (BSP) added |
| October 2017 | openembedded-core | First commit mentioning riscv |
| March 2018 | meta-riscv | HiFive Unleashed added |
| November 2018 | meta-riscv | qemuriscv32 BSP added |
| January 2019 | meta-riscv | Initial OpenSBI recipe added |
| June 2019 | openembedded-core | qemuriscv64 BSP moved from meta-riscv |
| March 2021 | openembedded-core | qemuriscv32 BSP moved from meta-riscv |
| April 2021 | meta-riscv | BeagleV BSP added |
| March 2022 | meta-riscv | Nezha D1-H added |
| July 2022 | meta-riscv | StarFive VisionFive BSP added |
| August 2022 | meta-riscv | Andes AE350 ax45mp BSP added |
| January 2023 | meta-riscv | StarFive VisionFive 2 BSP added |
| February 2023 | meta-riscv | MangoPi MQ-Pro BSP added |
| April 2023 | meta-riscv | PINE64 Star64 BSP added |
| October 2023 | meta-riscv | Milk-V Duo BSP added |
| January 2024 | meta-riscv | BeagleV-Ahead BSP added |
| February 2024 | meta-riscv | Milk-V Megrez BSP added |
| June 2025 | meta-riscv | OrangePi RV2/R2S BSPs added |
| September 2025 | openembedded-core | RVA23S64 profile becomes default in qemuriscv64 |
This is only a sample of the extensive and complicated work that many contributors have performed over the years, in both openembedded-core and meta-riscv. We thank them for their tremendous efforts in creating and making improvements to the RISC-V support in the Yocto Project, and we look forward to our continued work together.
(Almost) One Year Later: Successes and Challenges
Since September 2025, we have focused on two key areas:
- Triaging intermittent qemuriscv64 test failures in the Yocto Project’s CI/CD infrastructure (Autobuilder)
- Improving the meta-riscv layer, with tasks including adding new BSPs, enhancing existing support, ensuring that the layer meets Yocto Project standards, adding a hardware deprecation policy for future releases, and improving documentation
This has proved to be both challenging and rewarding work. The test failures seen in the Autobuilder are disproportionately high on qemuriscv64 (compared with other architectures), and manifest mainly when the host systems are under heavy load. The Yocto Project must test a large number of build configurations frequently, and this all-but-ensures that any given host system will feature at least some system loading when the tests run. Some failures can be mitigated by setting more generous test timeout limits, but the the ideal solutions involve further optimizations for RISC-V specifically, along with utilization of the latest RVA23-compliant hardware, which promises to improve performance.
In the meta-riscv layer, support is also evolving rapidly. The BSPs in the timeline section above primarily featured vendor-provided versions of the Linux Kernel, U-Boot, and so on; however, more recent work has added parallel BSPs which track mainline support, allowing developers to compare and contrast features as new upstream releases become available. Notable examples include additions of mainline BSPs for the SpacemiT K1 development boards (in particular, the OrangePi RV2, Muse Pi Pro, and BananaPi F3) and the ESWIN EBC77, all of which RISE has helped review, test, and extend. RISE is also actively working with SpacemiT on the very first BSP for the RVA23-compliant K3 Pico-ITX, which is being tested before final review.
To assist in tracking and maintaining meta-riscv, RISE has built basic CI/CD infrastructure using open-source software and with a hardware-in-the-loop component. Doing so allows us to perform nightly boot tests on various BSPs using the latest changes in Yocto, meaning that regressions are caught early, and it can also be used to test out new features we are developing. This has already proven successful in identifying bugs as new submissions arrive in the layer, and we hope that it will be an inspiration to others who are looking to automate their development workflow.
What’s Next?
Here are some things that RISE is working on over the coming months:
- The aforementioned BSP for the K3 Pico-ITX, which will continue to receive new features. This the “vendor” type for now, serving as a reference as K3 support improves in the upstream Linux Kernel, U-Boot, and elsewhere.
- Adding more RVA23 BSPs as additional platforms (K3 and otherwise) become available.
- Investigating further mitigations and/or optimizations of intermittent issues in the Yocto Project’s CI system.
- Continuing to assist with maintenance of meta-riscv and its BSPs, including consolidation of shared metadata and testing of new submissions to the layer.
- Discussing with the RISC-V and Yocto Project communities about goals for the future.
How to Get Involved
The Yocto Project is a collaborative effort, and it is always open to contributions, whether they’re from newcomers or industry experts. If you’d like to help improve RISC-V support in Yocto, you can start a discussion on GitHub, or visit the project’s contribution page for more info about how to contact us.
For more information on all of our work, come see our poster session “RISE and Yocto: Building a RISC-V Board Farm” at the RISC-V Summit in Bologna, June 8th-12th!
