RISE has completed its 2025 election for working group leads. Congratulations to all of the new (and reelected) leads, and a big Thank You to the outgoing leads! Your work has helped advance the RISC-V software ecosystem.
| Working Group | Lead/ Candidates | Bio |
| System Libraries | Ruinland Chuan-Tzu Tsai | Ruinland is an open-source software developer with six years of experience in system software/library projects. Currently serving at Andes Technology, his focus lies in operating systems, such as Android and C runtime libraries, and system libraries including musl-libc, glibc and other fundamental runtimes. He also possesses in-depth knowledge of Linux, FreeBSD, and is a veteran on bootstrapping Linux Distributions. |
| Simulator / Emulator | Daniel Barboza, Ventana | Daniel Barboza works with QEMU hardware emulation and virtualization since 2017. He has 10 years of PowerPC background and is working with RISC-V since early 2023. He’s also a committer in the libvirt project and has contributions in the Linux Kernel, most of them in the KVM subsystem.” |
| Language Runtimes | Mark Ryan, Rivos | Mark Ryan is a software engineer at Rivos Inc. He has a PhD in Computer Science and over 25 years of industry experience. Mark contributes to the riscv64 port of golang, leads the RISE wheel_builder project and works on RISE’s RISC-V Optimization Guide. Mark is an experienced assembly language programmer and is proficient in RISC-V, x86_64 and Z80. |
| Kernel KVM | Atish Patra, Rivos | Atish Patra has been an integral part of the RISC-V Linux ecosystem for nearly seven years, driving key innovations in open-source software. He has held multiple leadership roles, serving as chair or vice-chair of various technical groups under RISC-V International. For the past three years, he has led the Platform Runtime Services (PRS) TG, guiding its strategic direction and development. Atish has made significant contributions to the RISC-V Linux kernel, shaping its development in areas such as firmware, performance monitoring, virtualization, and confidential computing. Beyond his technical contributions, Atish is a vocal advocate for open-source innovation. Through his thought leadership and community engagement, he continues to evangelize and advance the RISC-V software ecosystem. |
| Firmware | Dhaval Sharma | I’m excited to join RISE as the Firmware Group Lead. With a long-standing background in firmware and system software, I’m looking forward to building on the progress already made in aligning various RISC-V firmware efforts.
I began my journey in the computing industry in 2004 as a firmware engineer at Intel, where I worked on BIOS development across multiple platforms. Over time, I played several roles at Intel, including Platform Architect, Server System Debug Lead, and other cross-functional leadership roles across client and server platforms. More recently, my work in RISE as a RISC-V firmware engineer has been technically fulfilling — particularly through projects like Universal Payload development for RISC-V platforms (and a few others). I’m truly looking forward to working with the RISE community and pushing things forward together. |
| Distro Integration | Brian Harrington, RedHat | Redbeard is currently the tech lead for RISC-V at Red Hat.
Noteworthy accomplishments in his previous roles include serving as Chief Architect at CoreOS, where he led the development of a cohesive vision across major projects like etcd, rkt, and Kubernetes. At Red Hat, he was Principal Product Manager for Red Hat OpenShift Service Mesh (Istio.io). Redbeard has been recognized for his contributions to the open-source community, particularly through his work on CoreOS technologies that were later open-sourced and contributed to the Linux Foundation and CNCF. In addition to his technical roles, redbeard has been involved in various community engagements, such as being a running the vendor area at DEF CON and Security Lead at Shmoocon, showcasing his commitment to security and community involvement. His expertise in distributed systems and open-source technologies has made significant impacts in the industry, contributing to the advancement of cloud-native applications and infrastructure. |
| TBDDebug and Profiling | TBD | TBD |
| Compilers and Toolchains | Petr Penzin, Tenstorrent | Petr is a compiler lead at Tenstorrent working on RISC-V CPU toolchain. He has worked on various compiler projects ranging from C and Fortran frontends to CPU backends, Web Runtimes, and HPC. Prior to joining Tenstorrent Petr has worked at Intel, Nvidia, and STMicroelectronics. |
| Security Software | Robin Randhawa, SiFive | I work for SiFive at Cambridge, UK, as a Senior Director for System Software Architecture. My primary focus is on Security and Safety design patterns. I work with CPU and system designers to ensure that SiFive’s software and hardware portfolio has best in class security and safety.
I’ve been in the systems software industry for 25 years and have worked for MIPS and Arm before my current job. I spent 15 years at Arm building up open source teams working on everything from firmware, the Linux kernel, Android and Vehicle Autonomy Control. I’m fond of operating system architecture and spend my spare time tinkering with FreeBSD, Redox and custom kernels on my collection of hardware. I’m very fond of the Rust programming language and also play with Nim, V and Zig. My dream is to define a custom CPU instruction set, design a CPU using it, build a simulator, a compiler toolchain and finally boot Linux on it. Not sure if I’ll ever get around to it but always aim high eh ? 🙂 When not nerding out (!) I like to travel, read, play video games and chill with my family. |
| Developer Infrastructure | Paul Walmsley, SiFive | A seasoned software architect and engineer, with over 15 years of experience leading cutting-edge system software development and architecture across a variety of platforms. Currently serving as Sr. Principal Engineer / Director of Software Architecture at SiFive, where they drive innovation in RISC-V-based systems. In addition to their engineering roles, they lead the Developer Infrastructure Working Group for RISE, where they were reelected after their first two-year term, demonstrating strong leadership and commitment to the community. |
| AI/ML | Leye Wang | Leye Wang is a tenured associate professor at Peking University, China. He also leads a technical group at the Beijing Institute of Open Source Chip (BOSC), specializing in optimizing open-source AI software for RISC-V architectures. His research centers on data-driven, AI-powered pervasive computing, with applications in IoT, embedded systems, etc. He has been consistently recognized among the Stanford/Elsevier Top 2% Most-Cited Scientists List from 2020 to 2024. |
